2015³â µ¿°èÇмú¹ßǥȸ
Current Result Document :
ÇѱÛÁ¦¸ñ(Korean Title) |
FBDtoVHDL: FPGA °³¹ßÀ» À§ÇÑ FBD·ÎºÎÅÍ VHDL ÀÚµ¿ º¯È¯ µµ±¸ |
¿µ¹®Á¦¸ñ(English Title) |
FBDtoVHDL: An automatic translation from FBD into VHDL for FPGA development |
ÀúÀÚ(Author) |
±èÀ翱
±èÀǼ·
À¯Áعü
ÀÌ¿µÁØ
ÃÖÁ¾±Õ
Jae-Yeob Kim
Eui-Sub Kim
Junbeom Yoo
Young Jun Lee
Jong-Gyun Choi
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¿ø¹®¼ö·Ïó(Citation) |
VOL 42 NO. 02 PP. 0461 ~ 0463 (2015. 12) |
Çѱ۳»¿ë (Korean Abstract) |
PLC (Programmable Logic Controller)´Â ¿øÀÚ·Â ¹ßÀü¼ÒÀÇ µðÁöÅÐ Á¦¾î½Ã½ºÅÛÀÇ °³¹ßÀ» À§ÇØ ³Î¸® »ç¿ëµÇ¾î¿ÔÁö¸¸ º¹À⼺ÀÇ Áõ°¡¿Í À¯Áöº¸¼ö ºñ¿ë µîÀÇ ¹®Á¦·Î ÀÎÇØ FPGA (Field Programmable Gate Array) ±â¹Ý Á¦¾î½Ã½ºÅÛÀÌ ´ë¾ÈÀ¸·Î ¶°¿À¸£°í ÀÖ´Ù. ÇÏÁö¸¸ FPGA ±â¹Ý Á¦¾î½Ã½ºÅÛÀ» °³¹ßÇϱâ À§Çؼ´Â PLC °³¹ßÀÚ°¡ »õ·Î¿î ¾ð¾î¸¦ »ç¿ëÇØ¾ß Çϸç, PLC °³¹ß¿¡ »ç¿ëµÈ ³ëÇÏ¿ì ¹× Áö½ÄÀÇ Àç»ç¿ëÀÌ ¾î·Æ´Ù´Â ¹®Á¦°¡ ÀÖ´Ù. º» ³í¹®¿¡¼´Â PLC ¼ÒÇÁÆ®¿þ¾î °³¹ßÀ» À§ÇÑ ¾ð¾î Áß ÇϳªÀÎ FBD (Function Block Diagram)¸¦ FPGA °³¹ßÀ» À§ÇÑ Çϵå¿þ¾î ±â¼ú ¾ð¾î Áß ÇϳªÀÎ VHDL·ÎÀÇ ÀÚµ¿ º¯È¯ ¹æ¹ýÀ» ¼Ò°³ÇÏ°í À̸¦ ±â¹ÝÀ¸·Î °³¹ßÇÑ ÀÚµ¿ º¯È¯ µµ±¸ÀÎ FBDtoVHDLÀ» ¼Ò°³ÇÑ´Ù. ±×¸®°í KNICS RPS BPÀÇ ·ÎÁ÷À» ÀÌ¿ëÇÑ ½ÇÇèÀ» ÅëÇØ FBDtoVHDL¸¦ ÀÌ¿ëÇØ º¯È¯ÇÑ VHDLÀÌ FBD¿Í µ¿ÀÏÇÑ ±â´ÉÀ» ¼öÇà ÇÏ´ÂÁö È®ÀÎÇÏ¿´´Ù. |
¿µ¹®³»¿ë (English Abstract) |
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